1. Field of the Invention
The present invention relates to an input and output circuit of a semiconductor device and method of operation thereof. More particularly, the present invention relates to an input and output circuit using a common input and output pin, adapted for, for example, a blind time setting circuit of a secondary battery protection circuit, and method of operation thereof.
2. Description of the Related Art
A secondary battery protection circuit used in a secondary battery unit detects an over-charge state, an over-discharge state and an over-current state of a secondary battery such as a lithium-ion battery. The secondary battery protection circuit performs an appropriate operation to protect the secondary battery in accordance with the detected state.
In the case when an over-charge state, over-discharge state or over-current state of the secondary battery is caused by a brief fluctuation in current or voltage, there is no need for the protection operation. Therefore, a secondary battery protection circuit generally includes a blind time setting circuit that prevents the execution of the protective operation during a predetermined time or blind time even when an over-charge state, over-discharge state or over-current state is detected.
When the secondary battery protection circuit is to be tested, the over-charge state, over-discharge state or over-current state needs to be maintained for a period of time that is longer than the blind time of the secondary battery protection circuit. That is, during a test operation it is not possible to know whether the protection operation properly takes place until the blind time elapses. Therefore, the time and expense of carrying out a test operation may be increased because of the wait time due to the blind time.
An example of a conventional secondary battery protection circuit is disclosed in U.S. Pat. No. 6,518,729, entitled “Secondary battery protection circuit capable of reducing time for functional test” (hereinafter “the '729 patent”). According to the '729 patent, in a test operation mode, the blind time setting circuit reduces the period of a clock signal generated by a clock generation circuit of the blind time setting circuit so that the blind time may be reduced.
FIG. 1 is a block diagram illustrating a conventional blind time setting circuit. Referring to FIG. 1, the conventional blind time setting circuit includes a clock generating circuit 110 and a delay time generating circuit 120. The clock generating circuit 110 generates a clock signal upon detecting an over-charge state, an over-discharge state or an over-current state of the secondary battery, and outputs the clock signal to the delay time generating circuit 120. When a test signal TEST having an active state is inputted to the clock generating circuit 110 in the test operation mode, the clock generating circuit 110 reduces the period of the clock signal generated thereby.
To reduce the period of the clock signal, the clock generating circuit 110 controls the current flowing through a capacitor in a plurality of charging/discharging units. In the test operation mode, the current flowing through the charging/discharging units may be increased to speed up the charging/discharging operation of the capacitor, resulting in a reduction in the period of the clock signal.
The delay time generating circuit 120 receives the clock signal generated by the clock generating circuit 110 and outputs instruction signals, i.e., over-charge instruction signals, over-discharge instruction signals, and over-current instruction signals. The respective blind times are preset for the over-charge state, over-discharge state and over-current state. In accordance with the instruction signals, the secondary battery protection circuit performs the protection operations. When the period of the clock signal generated by the clock generating circuit 110 is reduced in the test operation mode, the delay times of the respective instruction signals (i.e., blind times) outputted from the delay time generating circuit 120 are also reduced.
FIG. 2 is a circuit diagram illustrating the clock generating circuit 110 shown in FIG. 1. Referring to FIG. 2, the clock generating circuit 110 includes a plurality of charging/discharging units 210. Each of the charging/discharging units 210 includes a charging/discharging unit 211, a capacitor 213, a charging/discharging current source 215, a regulation transistor 217 and a test current source 219.
The regulation transistor 217 is turned on when the test signal TEST has an active state so that a test current ITEST flows through the regulation transistor 217. When the test signal TEST is inputted to the clock generating circuit 110, a current through a capacitor 213 increases, reducing the period of the clock signal generated by the clock generating circuit 110. Therefore, a test mode operation time may be reduced.
However, the clock generating circuit 110 shown in FIGS. 1 and 2 uses a separate input and output pin for the test mode operation using the reduced clock signal period. The use of separate input and output pins (I/O pins) may increase package size and cost. Moreover, additional current consumption may increase substrate noise that can degrade system performance.
In the clock generating circuit 110 shown in FIGS. 1 and 2, the clock signal outputted from the clock generating circuit 110 is provided to the delay time generating circuit 120, and the clock signal frequency of the clock signal generated by the clock generating circuit 110 cannot be checked externally. In a semiconductor device manufacturing process, it is necessary to measure the output clock signal of the clock generating circuit several times to perform a precise correction to a desired target value when the clock signal frequency of the clock generating circuit has a frequency error or if each of the charging/discharging units 210 has a delay time distribution. According to the '729 patent, the output clock signal of the clock generating circuit 110 is only measured through the delay time generating circuit 120 so that the measuring time may be increased. The clock generating circuit 110 shown in FIG. 2 further includes a separate test current source 219, thereby increasing hardware complexity.